{"title":"缓冲电荷再分布对硅基氮化镓衬底射频损耗和谐波失真的影响","authors":"Pieter Cardinael;Sachin Yadav;Bertrand Parvais;Jean-Pierre Raskin","doi":"10.1109/JEDS.2024.3386170","DOIUrl":null,"url":null,"abstract":"Understanding and mitigation of substrate RF losses and signal distortion are critical to enable high-performance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity \n<inline-formula> <tex-math>$({\\rho }_{eff})$ </tex-math></inline-formula>\n in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the \n<inline-formula> <tex-math>${\\rho }_{eff}$ </tex-math></inline-formula>\n degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in \n<inline-formula> <tex-math>${\\rho }_{eff}$ </tex-math></inline-formula>\n at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of \n<inline-formula> <tex-math>$2^{\\mathrm{ nd}}$ </tex-math></inline-formula>\n harmonic power of up to 5dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaN-on-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage (\n<inline-formula> <tex-math>$\\text{V}_{\\text {FB}}$ </tex-math></inline-formula>\n) of the Metal-Insulator-Semiconductor (MIS) structure. Free carrier transport across the buffer is shown to have the greatest contribution on the large time constants, highlighting the importance of vertical transport paths in GaN-on-Si stacks.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0000,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10495002","citationCount":"0","resultStr":"{\"title\":\"Effect of Buffer Charge Redistribution on RF Losses and Harmonic Distortion in GaN-on-Si Substrates\",\"authors\":\"Pieter Cardinael;Sachin Yadav;Bertrand Parvais;Jean-Pierre Raskin\",\"doi\":\"10.1109/JEDS.2024.3386170\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Understanding and mitigation of substrate RF losses and signal distortion are critical to enable high-performance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity \\n<inline-formula> <tex-math>$({\\\\rho }_{eff})$ </tex-math></inline-formula>\\n in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the \\n<inline-formula> <tex-math>${\\\\rho }_{eff}$ </tex-math></inline-formula>\\n degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in \\n<inline-formula> <tex-math>${\\\\rho }_{eff}$ </tex-math></inline-formula>\\n at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of \\n<inline-formula> <tex-math>$2^{\\\\mathrm{ nd}}$ </tex-math></inline-formula>\\n harmonic power of up to 5dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaN-on-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage (\\n<inline-formula> <tex-math>$\\\\text{V}_{\\\\text {FB}}$ </tex-math></inline-formula>\\n) of the Metal-Insulator-Semiconductor (MIS) structure. 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引用次数: 0
摘要
要实现高性能硅基氮化镓前端模块,了解并减少基底射频损耗和信号失真至关重要。虽然硅基氮化镓衬底的射频损耗以及由此导致的有效衬底电阻率$({\rho }_{eff})$下降的原因现在已被理解为在III-N生长过程中铝和镓原子向硅衬底的扩散,但上层III-N缓冲层对受压条件下${\rho }_{eff}$退化的影响仍不清楚。本文表明,当衬底在 50 V 下受压时,2 GHz 频率下的 ${\rho }_{eff}$ 在 1,000 秒内会发生高达 50%的变化。此外,在相同实验条件下进行的共面波导 (CPW) 大信号测量显示,2^{\mathrm{nd}}$谐波功率的变化高达 5dB。热激活应力和弛豫行为显示了掺杂 C 的层中存在陷阱的特征。借助简化的硅基氮化镓(GaN-on-Si)堆栈 TCAD 模型,我们将这种行为与掺杂 C 的缓冲器中缓慢的电荷再分布联系起来,这种再分布会持续改变金属-绝缘体-半导体(MIS)结构的平带电压($\{V}_{text {FB}}$)。跨缓冲器的自由载流子传输对大时间常数的贡献最大,这突出了硅基氮化镓叠层中垂直传输路径的重要性。
Effect of Buffer Charge Redistribution on RF Losses and Harmonic Distortion in GaN-on-Si Substrates
Understanding and mitigation of substrate RF losses and signal distortion are critical to enable high-performance GaN-on-Si front-end-modules. While the origin of RF losses and consequently a decreased effective substrate resistivity
$({\rho }_{eff})$
in GaN-on-Si substrates is now understood to be diffusion of Al and Ga atoms into the silicon substrate during III-N growth, the effect of upper III-N buffer layers on the
${\rho }_{eff}$
degradation under stressed conditions remains unclear. In this paper, we show that up to 50% variation in
${\rho }_{eff}$
at 2 GHz can take place over more than 1,000 s when the substrate is stressed at 50 V. Additionally, Coplanar Wave Guide (CPW) large-signal measurements under the same experimental conditions show a variation of
$2^{\mathrm{ nd}}$
harmonic power of up to 5dB. A thermally activated stress and relaxation behavior shows the signature of traps which are present in the C-doped layers. With the help of a simplified TCAD model of the GaN-on-Si stack, we link this behavior to slow charge redistribution in the C-doped buffer continuously modifying the flat-band voltage (
$\text{V}_{\text {FB}}$
) of the Metal-Insulator-Semiconductor (MIS) structure. Free carrier transport across the buffer is shown to have the greatest contribution on the large time constants, highlighting the importance of vertical transport paths in GaN-on-Si stacks.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.