{"title":"用于激光雷达应用的 8.5 ps 分辨率紧凑型相位域三角积分时数字转换器","authors":"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae","doi":"10.1109/LSSC.2024.3382594","DOIUrl":null,"url":null,"abstract":"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\n<inline-formula> <tex-math>$\\Delta \\Sigma$ </tex-math></inline-formula>\n) TDC. The proposed TDC operates in an incremental \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \n<inline-formula> <tex-math>$2000~\\mu \\text{m}~^{\\mathrm{ 2}}$ </tex-math></inline-formula>\n. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"127-130"},"PeriodicalIF":2.2000,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications\",\"authors\":\"Yoondeok Na;Myung-Jae Lee;Youngcheol Chae\",\"doi\":\"10.1109/LSSC.2024.3382594\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD\\n<inline-formula> <tex-math>$\\\\Delta \\\\Sigma$ </tex-math></inline-formula>\\n) TDC. The proposed TDC operates in an incremental \\n<inline-formula> <tex-math>$\\\\Delta \\\\Sigma $ </tex-math></inline-formula>\\n manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of \\n<inline-formula> <tex-math>$2000~\\\\mu \\\\text{m}~^{\\\\mathrm{ 2}}$ </tex-math></inline-formula>\\n. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"7 \",\"pages\":\"127-130\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2024-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10480694/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10480694/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A Compact Phase-Domain Delta–Sigma Time-to-Digital Converter With 8.5-ps Resolution for LiDAR Applications
This letter introduces a compact, high-resolution time-to-digital converter (TDC) for lidar applications. In contrast to a conventional histogram-based peak detection method, this letter proposes a mean detection method using a highly digitized phase-domain delta–sigma (PD
$\Delta \Sigma$
) TDC. The proposed TDC operates in an incremental
$\Delta \Sigma $
manner for a compact implementation and utilizing a digital integrator as a loop filter that facilitates an extended counting, resulting in significantly improved resolution. By utilizing a dual gated-ring oscillator (GRO) structure, time-quantization noise due to a residue phase of GRO is effectively mitigated. To address the issue of single-photon avalanche diode (SPAD) signals due to their stochastic nature, a dual time window is proposed to compensate for counting error when SPAD trigger missing occurs. Fabricated in a 65-nm CMOS process, the prototype TDC occupies only an area of
$2000~\mu \text{m}~^{\mathrm{ 2}}$
. It achieves a noise level of 27.6 ps for the number of cycles of 32. When the cycle is 1000, it achieves a maximum integral nonlinearity (INL) of 80 ps (+53 ps/-27 ps) with a resolution of 8.5 ps.