Amitesh Sridharan;Jyotishman Saikia;Anupreetham;Fan Zhang;Jae-Sun Seo;Deliang Fan
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引用次数: 0
摘要
我们展示了一个全数字乘法累加(MAC)内存计算(IMC)宏,它是迄今为止速度最快的灵活精度整数 MAC 之一。该设计采用了全新的位并行架构,该架构由一个能够进行四次 AND 运算的 10T 位元组和一个分解精度数据流实现,该数据流减少了移位累加运算的次数,从而将总体加法器硬件成本降低了 1.57 美元/次,同时保持了所有支持精度的 100% 利用率。它还采用了节省进位的加法器树,节省了 21% 的加法器硬件。在1bW:1bI、1bW:4bI、4bW:4bI和8bW:8bI MAC中,28纳米原型芯片的速度比先前的SoTA分别提高了2.6美元、10.8美元、2.42美元和3.22美元。
PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs
We present a fully digital multiply and accumulate (MAC) in-memory computing (IMC) macro demonstrating one of the fastest flexible precision integer-based MACs to date. The design boasts a new bit-parallel architecture enabled by a 10T bit-cell capable of four AND operations and a decomposed precision data flow that decreases the number of shift–accumulate operations, bringing down the overall adder hardware cost by
$1.57\times $
while maintaining 100% utilization for all supported precision. It also employs a carry save adder tree that saves 21% of adder hardware. The 28-nm prototype chip achieves a speed-up of
$2.6\times $
,
$10.8\times $
,
$2.42\times $
, and
$3.22\times $
over prior SoTA in 1bW:1bI, 1bW:4bI, 4bW:4bI, and 8bW:8bI MACs, respectively.