Reverse Charge Injection Dual-Gate Synaptic Transistors for Effective Weight Update

Reverse charge injection (RCI) dual-gate synaptic transistors and their effective weight update method are proposed. First, the structural features of the proposed RCI dual-gate synaptic transistors are discussed in comparison with our previous work. Second, the weight update efficiency of the proposed synaptic transistors is discussed by analyzing the coupling capacitance components, which determine the electric field distribution across the tunneling and blocking oxides. Consequently, the program voltage and pulse width are reduced by 56.4% and 99.0%, respectively. The power consumption for the weight update operation is lowered by 99.6%. In addition, the anti-back-tunneling effect resulting from the low erase voltage is discussed. Third, the weight update conditions of the proposed synaptic transistors are optimized by adjusting the bottom gate length. Fourth, the proposed synaptic transistors implement 16 stable states (32 states with inhibitory synapses) and a fairly linear weight update by using both the increment step pulse program (ISPP) and increment step pulse erase (ISPE). Finally, the PGM/ERS operation of target cell and inhibit operation of surrounding cells are verified in RCI dual-gate synaptic transistor-based 2 × 2 NOR-type array.