{"title":"通过二维排列硅显示驱动器实现单片集成 CAAC-OS FET 和硅 CMOS 的 OLED 微型显示器","authors":"Munehiro Kozuma;Yusuke Komura;Shoki Miyata;Yuki Okamoto;Yuki Tamatsukuri;Hiroki Inoue;Toshihiko Saito;Hidetomo Kobayashi;Tatsuya Onuki;Yuichi Yanagisawa;Toshihiko Takeuchi;Yutaka Okazaki;Hitoshi Kunitake;Daiki Nakamura;Takaaki Nagata;Yasumasa Yamane;Makoto Ikeda;Shunpei Yamazaki","doi":"10.1109/JEDS.2024.3366938","DOIUrl":null,"url":null,"abstract":"We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS display drivers can be arranged two-dimensionally by monolithically stacking \n<inline-formula> <tex-math>${c}$ </tex-math></inline-formula>\n-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs over Si CMOS. A CAAC-OS FET exhibits a higher withstand voltage than a SiFET of the same size, enabling considerable pixel area reduction. The CAAC-OS FET can be driven even at a low refresh rate owing to its extremely low off-state current, making it an ideal choice for constructing pixel circuits. This integration of CAAC-OS FETs empowers our display system to offer enhanced resolution and reduced power consumption. The two-dimensionally arranged drivers have two features. (1) Si drivers can be arranged in two-dimensional driver blocks with a desired size, which provides flexibility to increase the number of driver stages and adjust resolution and frame rates for each driver block via logic processing. (2) The circuit performance of the system can be changed to prioritize frame rate and power consumption, which have a trade-off relation, of the driver by providing a redundant circuit in the driver. To demonstrate these features, we fabricated a prototype display and confirmed that our driver had a power consumption of 1,094.96 mW at 30 Gbps in a normal mode and 524.55 mW at 3.75 Gbps in a foveated rendering (FR) mode, revealing a 52% reduction in power consumption in the FR mode. This technology is expected to achieve high-frame-rate performance, which has been difficult to achieve in conventional microdisplays.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0000,"publicationDate":"2024-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10439975","citationCount":"0","resultStr":"{\"title\":\"OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers\",\"authors\":\"Munehiro Kozuma;Yusuke Komura;Shoki Miyata;Yuki Okamoto;Yuki Tamatsukuri;Hiroki Inoue;Toshihiko Saito;Hidetomo Kobayashi;Tatsuya Onuki;Yuichi Yanagisawa;Toshihiko Takeuchi;Yutaka Okazaki;Hitoshi Kunitake;Daiki Nakamura;Takaaki Nagata;Yasumasa Yamane;Makoto Ikeda;Shunpei Yamazaki\",\"doi\":\"10.1109/JEDS.2024.3366938\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS display drivers can be arranged two-dimensionally by monolithically stacking \\n<inline-formula> <tex-math>${c}$ </tex-math></inline-formula>\\n-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs over Si CMOS. A CAAC-OS FET exhibits a higher withstand voltage than a SiFET of the same size, enabling considerable pixel area reduction. The CAAC-OS FET can be driven even at a low refresh rate owing to its extremely low off-state current, making it an ideal choice for constructing pixel circuits. This integration of CAAC-OS FETs empowers our display system to offer enhanced resolution and reduced power consumption. The two-dimensionally arranged drivers have two features. (1) Si drivers can be arranged in two-dimensional driver blocks with a desired size, which provides flexibility to increase the number of driver stages and adjust resolution and frame rates for each driver block via logic processing. (2) The circuit performance of the system can be changed to prioritize frame rate and power consumption, which have a trade-off relation, of the driver by providing a redundant circuit in the driver. To demonstrate these features, we fabricated a prototype display and confirmed that our driver had a power consumption of 1,094.96 mW at 30 Gbps in a normal mode and 524.55 mW at 3.75 Gbps in a foveated rendering (FR) mode, revealing a 52% reduction in power consumption in the FR mode. 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引用次数: 0
摘要
我们开发了一种有机发光二极管(OLED)/氧化物半导体(OS)/硅(Si)显示器,其中硅 CMOS 显示驱动器可通过在硅 CMOS 上单片堆叠{c}$ - 轴对齐晶体氧化物半导体(CAAC-OS)场效应晶体管进行二维排列。与相同尺寸的硅场效应晶体管相比,CAAC-OS 场效应晶体管具有更高的耐压,从而大大缩小了像素面积。CAAC-OS FET 的离态电流极低,即使在低刷新率下也能驱动,因此是构建像素电路的理想选择。这种 CAAC-OS FET 的集成使我们的显示系统能够提供更高的分辨率和更低的功耗。二维排列的驱动器有两个特点。(1) Si 驱动器可按所需尺寸排列成二维驱动器块,这为增加驱动器级数以及通过逻辑处理调整每个驱动器块的分辨率和帧速率提供了灵活性。(2) 通过在驱动器中提供冗余电路,可以改变系统的电路性能,优先考虑具有权衡关系的帧速率和驱动器功耗。为了演示这些功能,我们制作了一个显示器原型,并证实我们的驱动器在普通模式下 30 Gbps 的功耗为 1,094.96 mW,而在 3.75 Gbps 画面渲染(FR)模式下的功耗为 524.55 mW,在 FR 模式下功耗降低了 52%。这项技术有望实现传统微显示器难以达到的高帧速率性能。
OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers
We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS display drivers can be arranged two-dimensionally by monolithically stacking
${c}$
-axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs over Si CMOS. A CAAC-OS FET exhibits a higher withstand voltage than a SiFET of the same size, enabling considerable pixel area reduction. The CAAC-OS FET can be driven even at a low refresh rate owing to its extremely low off-state current, making it an ideal choice for constructing pixel circuits. This integration of CAAC-OS FETs empowers our display system to offer enhanced resolution and reduced power consumption. The two-dimensionally arranged drivers have two features. (1) Si drivers can be arranged in two-dimensional driver blocks with a desired size, which provides flexibility to increase the number of driver stages and adjust resolution and frame rates for each driver block via logic processing. (2) The circuit performance of the system can be changed to prioritize frame rate and power consumption, which have a trade-off relation, of the driver by providing a redundant circuit in the driver. To demonstrate these features, we fabricated a prototype display and confirmed that our driver had a power consumption of 1,094.96 mW at 30 Gbps in a normal mode and 524.55 mW at 3.75 Gbps in a foveated rendering (FR) mode, revealing a 52% reduction in power consumption in the FR mode. This technology is expected to achieve high-frame-rate performance, which has been difficult to achieve in conventional microdisplays.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.