Hot-carrier induced degradation of Ge/STI interfaces in Ge-on-Si junction devices

The degradation of Ge junctions epitaxially grown within shallow trench isolation (STI) on Si is investigated for geometries with different Area-to-Perimeter (A/P) ratios under constant-voltage stress. We show that the reverse-bias relative current shift ($\Delta I\left(t\right)/I_0$) exhibits a two component behaviour ascribed to the interplay between charge trapping in (pre-existing) traps and generation of new defects mostly along the perimeter of the junctions (Ge/STI interfaces), which affect the trap assisted tunnelling (TAT) leakage current. A semi-empirical model of the degradation kinetics is proposed, allowing to decouple the role of the two individual degradation mechanisms. The insights and the methodology presented are expected to be of relevance for Ge-on-Si active components for Silicon Photonics applications.