{"title":"5G+ 和生物医学应用中的新型混合快速傅立叶变换处理器","authors":"R. Priyadharsini, S. Sasipriya","doi":"10.1016/j.micpro.2024.105022","DOIUrl":null,"url":null,"abstract":"<div><p>To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mn>2</mn></msup></mrow></math></span>), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.</p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":"105 ","pages":"Article 105022"},"PeriodicalIF":1.9000,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications\",\"authors\":\"R. Priyadharsini, S. Sasipriya\",\"doi\":\"10.1016/j.micpro.2024.105022\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mn>2</mn></msup></mrow></math></span>), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.</p></div>\",\"PeriodicalId\":49815,\"journal\":{\"name\":\"Microprocessors and Microsystems\",\"volume\":\"105 \",\"pages\":\"Article 105022\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2024-01-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microprocessors and Microsystems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0141933124000176\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessors and Microsystems","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0141933124000176","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications
To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 ), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.
期刊介绍:
Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC).
Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.