{"title":"栅源/漏极重叠对 FeFET 的影响","authors":"Changha Kim , Dong-Oh Kim , Woo Young Choi","doi":"10.1016/j.sse.2024.108862","DOIUrl":null,"url":null,"abstract":"<div><p>The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (<em>L</em><sub>ov</sub>’s) and doping concentrations of the gate-source/drain overlap region (<em>D</em><sub>ov</sub>’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As <em>L</em><sub>ov</sub> and <em>D</em><sub>ov</sub> increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (<em>C</em><sub>ov,gate-S/D</sub>) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs.</p></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":null,"pages":null},"PeriodicalIF":1.4000,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Influence of gate-source/drain overlap on FeFETs\",\"authors\":\"Changha Kim , Dong-Oh Kim , Woo Young Choi\",\"doi\":\"10.1016/j.sse.2024.108862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (<em>L</em><sub>ov</sub>’s) and doping concentrations of the gate-source/drain overlap region (<em>D</em><sub>ov</sub>’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As <em>L</em><sub>ov</sub> and <em>D</em><sub>ov</sub> increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (<em>C</em><sub>ov,gate-S/D</sub>) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs.</p></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2024-01-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S003811012400011X\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S003811012400011X","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (Lov’s) and doping concentrations of the gate-source/drain overlap region (Dov’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As Lov and Dov increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (Cov,gate-S/D) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs.
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It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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