具有按需无源谐波抑制功能的混频器优先接收器

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-01-09 DOI:10.1109/LSSC.2024.3351671

Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier

{"title":"具有按需无源谐波抑制功能的混频器优先接收器","authors":"Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier","doi":"10.1109/LSSC.2024.3351671","DOIUrl":null,"url":null,"abstract":"This letter presents a mixer-first RF receiver that: 1) nominally operates in a low-NF \n<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\n-path filter mode; 2) features an on-chip harmonic blocker detection circuit running in the background; 3) switches to a harmonic rejection mode upon detection of harmonic content; and 4) passively rejects harmonic blockers through a current-mode circuit that uses resistor sizing to set the amplitude of each path, but with capacitive termination to minimize conversion loss to 1.9 dB while providing a sharp, down-converted filter response. Implemented in 65nm CMOS, the receiver achieves 36/40-dB HR3/5,+21 dBm IIP3, +1 dBm blocker 1-dB compression point (B1dB) and 4/8-dB NF while consuming 10–23 mW.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"7 ","pages":"46-49"},"PeriodicalIF":2.2000,"publicationDate":"2024-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Mixer-First Receiver With On-Demand Passive Harmonic Rejection\",\"authors\":\"Hongyu Lu;Hossein Rahmanian Kooshkaki;Patrick P. Mercier\",\"doi\":\"10.1109/LSSC.2024.3351671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a mixer-first RF receiver that: 1) nominally operates in a low-NF \\n<inline-formula> <tex-math>$N$ </tex-math></inline-formula>\\n-path filter mode; 2) features an on-chip harmonic blocker detection circuit running in the background; 3) switches to a harmonic rejection mode upon detection of harmonic content; and 4) passively rejects harmonic blockers through a current-mode circuit that uses resistor sizing to set the amplitude of each path, but with capacitive termination to minimize conversion loss to 1.9 dB while providing a sharp, down-converted filter response. Implemented in 65nm CMOS, the receiver achieves 36/40-dB HR3/5,+21 dBm IIP3, +1 dBm blocker 1-dB compression point (B1dB) and 4/8-dB NF while consuming 10–23 mW.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"7 \",\"pages\":\"46-49\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2024-01-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10384702/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10384702/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

这封信介绍了一种混频器优先射频接收器，它具有以下特点1) 名义上以低 NF $N$ 路径滤波器模式运行；2) 具有在后台运行的片上谐波阻断器检测电路；3) 在检测到谐波内容时切换到谐波抑制模式；4) 通过电流模式电路被动地抑制谐波阻断器，该电路使用电阻器大小来设置每条路径的振幅，但采用电容终端将转换损耗降至 1.9 dB，同时提供尖锐的下变频滤波器响应。该接收器采用 65nm CMOS 工艺，实现了 36/40 dB HR3/5、+21 dBm IIP3、+1 dBm Blocker 1 dB 压缩点 (B1dB) 和 4/8 dB NF，功耗为 10-23 mW。

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A Mixer-First Receiver With On-Demand Passive Harmonic Rejection

This letter presents a mixer-first RF receiver that: 1) nominally operates in a low-NF

$N$

-path filter mode; 2) features an on-chip harmonic blocker detection circuit running in the background; 3) switches to a harmonic rejection mode upon detection of harmonic content; and 4) passively rejects harmonic blockers through a current-mode circuit that uses resistor sizing to set the amplitude of each path, but with capacitive termination to minimize conversion loss to 1.9 dB while providing a sharp, down-converted filter response. Implemented in 65nm CMOS, the receiver achieves 36/40-dB HR3/5,+21 dBm IIP3, +1 dBm blocker 1-dB compression point (B1dB) and 4/8-dB NF while consuming 10–23 mW.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量