Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices

In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.