Antonio J. Sánchez , Yubal Barrios , Lucana Santos , Roberto Sarmiento
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引用次数: 0
摘要
系统级设计利用构建模块(称为软 IP 核)来构建复杂的开发项目。使用这些 IP 核可以缩短设计和验证时间,还可以节约成本。然而,由于第三方 IP 核的组织、分配和管理缺乏标准化,导致数据库异构,因此使用第三方 IP 核往往会遇到困难。大多数情况下,系统开发人员需要描述一些额外的代码,以实现 IP 内核的集成、验证和确认,而这些代码并不作为 IP 内核发布的一部分。这意味着需要对每个 IP 核有深入的了解,学习曲线往往很高。Abeto 是一种用于 IP 核数据库管理的新软件工具。它可以通过一套统一的指令或命令,轻松集成和使用用 VHDL 描述的异构 IP 核。为此,Abeto 要求每个 IP 核提供一些有关其封装和如何使用 IP 的侧面信息。目前,Abeto 为一系列著名的 EDA 工具提供支持,并已成功应用于欧洲航天局的 IP 内核组合进行基准测试。为了证明其性能,我们提供了这些 IP 核在新型 NanoXplore BRAVE FPGA 系列上的映射结果。
Abeto: An automated benchmarking tool to manage heterogeneous IP core databases
System-level design makes use of building blocks, known as soft IP cores, to build complex developments. The usage of these IP cores allows to reduce design and verification time, and also to save costs. However, the use of third-party IP cores tends to present difficulties because of a lack of standardization in their organization, distribution and management, which derive in heterogeneous databases. Most of the time, system developers need to describe some additional code to enable the integration, verification and validation of the IP core, which is not available as part of their distribution. This implies acquiring a deep knowledge of each IP core, often with a large learning curve.
In this work Abeto is presented, a new software tool for IP core databases management. It allows to easily integrate and use a heterogeneous group of IP cores, described in VHDL, with a unified set of instructions or commands. In order to do so, Abeto requires from every IP core some side information about its packaging and how to operate with the IP. Currently, Abeto provides support for a set of well-known EDA tools and has been successfully applied to the European Space Agency portfolio of IP cores for benchmarking purposes. To demonstrate its performance, mapping results for these IP cores on the novel NanoXplore BRAVE FPGA family are provided.
期刊介绍:
Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC).
Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.