采用 RRAM 寻址的 40 纳米内存计算宏程序 IR 下降和关态电流

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2023-12-01 DOI:10.1109/LSSC.2023.3338212

Samuel D. Spetalnick;Muya Chang;Shota Konno;Brian Crafton;Ashwin Sanjay Lele;Win-San Khwa;Yu-Der Chih;Meng-Fan Chang;Arijit Raychowdhury

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引用次数: 0

摘要

这封信介绍了一种使用电阻式随机存取存储器（RRAM）的模拟电流求和内存计算宏。读出跨阻抗放大器利用位线（BL）和源线（SL）新增传感路径的差分输入进行偏移抵消，以最大限度地减小通道到通道（ch./ch.）增益误差，同时减轻 BL、SL 和多路复用器（MUX）中的 IR 下降。模数转换器 (ADC) 采用动态偏移抵消技术来消除通道/通道之间的增益误差。模数转换器（ADC）采用动态偏移抵消技术，以消除由 RRAM 关态电流引起的 ADC 本征偏移和误差。使用代工 RRAM 在 40 纳米 CMOS 中实现的 64KB 宏面积为 0.0263 平方毫米，通道/通道增益标准偏差为 1.9%，每字线 IR 降为 0.004%，1.1 V 效率为 7.8-58.8 TOPS/W。

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A 40-nm Compute-in-Memory Macro With RRAM Addressing IR Drop and Off-State Current

This letter describes an analog current-summing compute-in-memory macro using resistive random-access memory (RRAM). The readout transimpedance amplifiers use offset canceling with differential inputs from added sensing paths for the bitline (BL) and sourceline (SL) to minimize channel-to-channel (ch./ch.) gain error while mitigating IR drop in the BL, SL, and multiplexors (MUXes). The analog-to-digital converters (ADCs) use dynamic offset cancelation to remove ch./ch. ADC intrinsic offset and error due to RRAM off-state current. The 64Kb macro implemented with foundry RRAM in 40-nm CMOS has an area of 0.0263 mm2, ch./ch. gain std. dev. of 1.9%, IR drop per-wordline of 0.004%, and 1.1 V efficiency of 7.8–58.8 TOPS/W.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量