通过电流钳位提高退激效率的 SiGe BiCMOS D 波段异频功率混频器

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2023-11-15 DOI:10.1109/LSSC.2023.3332766

Andrea Bilato;Ibrahim Petricli;Andrea Mazzanti

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引用次数: 0

摘要

提出了一种55纳米SiGe BiCMOS的d波段功率上转换器。将开关四极体的低输出电阻确定为d波段混频器功率产生的限制因素，并将共基晶体管堆叠以增强输出功率。此外，利用电流箝位机构来缩放电源的平均电流与输出功率，提高了回退效率。实验结果表明，${P_{\mathrm{sat}}}\，\，{=}$ 6.3 dBm和${oP_{\mathrm{1dB}}}\，\，{=}$ 4.5 dBm在140 GHz下的效率分别为3.05%和2.47%。2v电源的功耗从静态点的70mw上升到$ {P_{\ mathm {sat}} $的140mw。测量的输出功率和效率与以前的工作相比是良好的。

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SiGe BiCMOS D-Band Heterodyne Power Mixer With Back-Off Efficiency Enhanced by Current Clamping

A D-band power upconverter in a 55-nm SiGe BiCMOS is presented. The low-output resistance of a switching quad is identified as a limiting factor to mixer power generation in D-band, and common-base transistors are stacked for output power enhancement. Moreover, the current clamping mechanism is exploited to scale the average supply current with output power, improving the efficiency in back-off. Experimental results demonstrate

$ {P_{\mathrm{ sat}}}\,\,{=}$

6.3 dBm and

${oP_{\mathrm{ 1dB}}}\,\,{=}$

4.5 dBm at 140 GHz, with efficiency of 3.05% and 2.47%, respectively. The power consumption, from a 2-V supply, rises from 70 mW at the quiescent point to 140 mW at

$ {P_{\mathrm{ sat}}}$

. The measured output power and efficiency compare favorably against previous works.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量