基于三角积分调制器可变分辨率激活的 SRAM 内存计算宏程序

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2023-10-24 DOI:10.1109/LSSC.2023.3327213

Vasundhara Damodaran;Ziyu Liu;Jian Meng;Jae-Sun Seo;Arindam Sanyal

{"title":"基于三角积分调制器可变分辨率激活的 SRAM 内存计算宏程序","authors":"Vasundhara Damodaran;Ziyu Liu;Jian Meng;Jae-Sun Seo;Arindam Sanyal","doi":"10.1109/LSSC.2023.3327213","DOIUrl":null,"url":null,"abstract":"This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit \n<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>\n modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4–138.6 TOPS/W.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":"6 ","pages":"293-296"},"PeriodicalIF":2.2000,"publicationDate":"2023-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation\",\"authors\":\"Vasundhara Damodaran;Ziyu Liu;Jian Meng;Jae-Sun Seo;Arindam Sanyal\",\"doi\":\"10.1109/LSSC.2023.3327213\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit \\n<inline-formula> <tex-math>$\\\\Delta \\\\Sigma $ </tex-math></inline-formula>\\n modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4–138.6 TOPS/W.\",\"PeriodicalId\":13032,\"journal\":{\"name\":\"IEEE Solid-State Circuits Letters\",\"volume\":\"6 \",\"pages\":\"293-296\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2023-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Solid-State Circuits Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10293176/\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10293176/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

摘要

这封信介绍了一种基于 SRAM 的内存计算 (CIM) 宏，它使用 1 位 $\Delta \Sigma $ 调制器将输入和输出激活转换为二进制脉冲波形。与电流域 SRAM CIM 宏相比，SRAM 宏使用开关电容器进行矢量矩阵乘法，加上二进制输入激活，提高了线性度，并允许重新配置激活分辨率。所提出的宏采用 65 纳米制造，并在 MNIST 和 CIFAR-10 数据集上进行了基准测试，准确率分别为 98.67% 和 89.85%，能效范围为 15.4-138.6 TOPS/W。

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SRAM In-Memory Computing Macro With Delta-Sigma Modulator-Based Variable-Resolution Activation

This letter presents an SRAM-based compute-in-memory (CIM) macro that uses 1-bit

$\Delta \Sigma $

modulators to convert input and output activations to binary pulse waveform. The SRAM macro uses switched-capacitors for vector matrix multiplications and together with binary input activation improves linearity compared to current-domain SRAM CIM macros and allows reconfigurable activation resolution. The proposed macro is fabricated in 65 nm and benchmarked on MNIST and CIFAR-10 datasets with accuracies of 98.67% and 89.85%, respectively, with energy-efficiency in the range of 15.4–138.6 TOPS/W.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量