A New Scheme for Low-Power, Low-Latency, and Interferer-Tolerant Wake-Up Receivers

This letter presents a new approach to low-power, low-latency, and frequency-selective wake-up receivers. A novel architecture is introduced to achieve frequency domain selectivity, including analog techniques, that enable data detection without the need for power-hungry digital processing. A two-mode duty cycling is also utilized, which helps reduce the power consumption of the receiver significantly with negligible latency. A prototype of the proposed receiver is fabricated and verified in a 180-nm CMOS process. The fabricated chipset achieves a sensitivity of −84.9 dBm with 4.32-ms wake-up latency and drains an average current of $12.2 ~\mu \text{A}$ . Interference tests show an outstanding signal-to-interference ratio (SIR) of −42/−49/−51 dB at 0.11%/0.22%/0.33% frequency offset from the carrier, confirming the interference immunity of the proposed design.