CMOS lsi测试台后处理损伤评估结构

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI:10.1109/ICMTS.2019.8730991

Y. Okamoto, Ayako Mizushima, Naoto Usami, Jun Kinoshita, A. Higo, Y. Mita

{"title":"CMOS lsi测试台后处理损伤评估结构","authors":"Y. Okamoto, Ayako Mizushima, Naoto Usami, Jun Kinoshita, A. Higo, Y. Mita","doi":"10.1109/ICMTS.2019.8730991","DOIUrl":null,"url":null,"abstract":"We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of $\\pmb{16\\times 16}$ arrayed PMOSFETs designed with 0.6 $\\pmb{\\mu}\\mathbf{m}$ CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of $I_{\\mathrm{d}}-V_{\\mathrm{g}}$ were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place post-processed bond pads over an LSI chip.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs\",\"authors\":\"Y. Okamoto, Ayako Mizushima, Naoto Usami, Jun Kinoshita, A. Higo, Y. Mita\",\"doi\":\"10.1109/ICMTS.2019.8730991\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of $\\\\pmb{16\\\\times 16}$ arrayed PMOSFETs designed with 0.6 $\\\\pmb{\\\\mu}\\\\mathbf{m}$ CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of $I_{\\\\mathrm{d}}-V_{\\\\mathrm{g}}$ were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place post-processed bond pads over an LSI chip.\",\"PeriodicalId\":333915,\"journal\":{\"name\":\"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2019.8730991\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2019.8730991","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

我们评估了额外键垫后处理引起的MOSFET特性的潜在退化。在维修和测试中，焊盘用作稳定的电气连接。测试结构由$\pmb{16\times 16}$阵列pmosfet组成，采用0.6 $\pmb{\mu}\mathbf{m}$ CMOS技术设计。使用硅阴影掩膜将铝垫沉积在阵列结构上，随后进行导线键合。比较后处理前后$I_{\mathrm{d}}-V_{\mathrm{g}}$的特性。结果表明，后处理不影响mosfet的特性，因此可以用于在LSI芯片上放置后处理的键合垫。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Damage Assessment Structure of Test-Pad Post-Processing on CMOS LSIs

We assessed potential degradation of MOSFET characteristics induced by post-processing of extra bond pads. The pads are used as stable electrical connections in repairing and test. The test structure consists of $\pmb{16\times 16}$ arrayed PMOSFETs designed with 0.6 $\pmb{\mu}\mathbf{m}$ CMOS technology. An aluminum pad is deposited on the arrayed structure using a silicon shadow mask, and wire bonding is performed subsequently. The characteristics of $I_{\mathrm{d}}-V_{\mathrm{g}}$ were compared before and after the post-process. The result indicates that the post-processing does not affect the characteristics of MOSFETs, and therefore it can be used to place post-processed bond pads over an LSI chip.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)

自引率

0.00%

发文量