A Study of Test Throughput Analysis on Capacitance Measurement of Parallel Test Structures Using LCR and Direct Charge based Instruments

Advancement in technology scaling has enabled further integration of additional structures per area. While the direct benefits of improved performance in smaller packaging is achieved, the test content per structure has increased for quicker and better yield learning, ultimately driving up test time and cost. Parallel testing where multiple devices can be measured synchronously or asynchronously has shown results in addressing such high test demand [1] [2]. In this paper, we discuss capacitance measurement using traditional LCR meter and direct charge measurement (DCM) hardware [3] on advanced technology nodes. The LCR meter is a shared resource, whereas DCM is a per-pin based architecture of capacitance measurement, enabled for higher throughput. Recent studies [3] [4] [7] comparing DCM based hardware to LCR meters can fall short when devices show higher leakage especially during the initial phase of technology development. We present how an improved DCM hardware [6] helps in better overall correlation to LCR while maintaining throughput. Also, the structures designed for parallel test (DFPT), contribute to higher throughput when tested using DCM.