{"title":"3D集成的工艺开发:用于高密度芯片间互连的导电晶圆键合","authors":"Chongshen Song, Wenqi Zhang, D. Shangguan","doi":"10.1109/LTB-3D.2014.6886143","DOIUrl":null,"url":null,"abstract":"This paper discusses the application of conductive wafer bonding, especially wafer level hybrid Cu-Cu bonding, for realizing high density inter-chip interconnection. 3D integration process using conductive wafer bonding and the test vehicle for bonding process evaluation are described. Different pre-bonding surface treatment methods and bonding procedures are studied and compared for yield and throughput optimization.","PeriodicalId":123514,"journal":{"name":"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Process development for 3D integration: Conductive wafer bonding for high density inter-chip interconnection\",\"authors\":\"Chongshen Song, Wenqi Zhang, D. Shangguan\",\"doi\":\"10.1109/LTB-3D.2014.6886143\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the application of conductive wafer bonding, especially wafer level hybrid Cu-Cu bonding, for realizing high density inter-chip interconnection. 3D integration process using conductive wafer bonding and the test vehicle for bonding process evaluation are described. Different pre-bonding surface treatment methods and bonding procedures are studied and compared for yield and throughput optimization.\",\"PeriodicalId\":123514,\"journal\":{\"name\":\"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LTB-3D.2014.6886143\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LTB-3D.2014.6886143","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Process development for 3D integration: Conductive wafer bonding for high density inter-chip interconnection
This paper discusses the application of conductive wafer bonding, especially wafer level hybrid Cu-Cu bonding, for realizing high density inter-chip interconnection. 3D integration process using conductive wafer bonding and the test vehicle for bonding process evaluation are described. Different pre-bonding surface treatment methods and bonding procedures are studied and compared for yield and throughput optimization.