Y. Ito, T. Fukushima, K. Lee, K. Choki, T. Tanaka, M. Koyanagi
{"title":"表面张力驱动的VCSEL芯片自组装键合,实现三维和异质集成","authors":"Y. Ito, T. Fukushima, K. Lee, K. Choki, T. Tanaka, M. Koyanagi","doi":"10.1109/LTB-3D.2014.6886154","DOIUrl":null,"url":null,"abstract":"Self-assembly with liquid surface tension was applied to tiny chips that were difficult to manipulate. Dummy chips that mimics VCSEL were aligned toward hydrophilic sites surrounding a hydrophobic area on an Si interposer. The alignment accuracies were 0 and -2.0 μm in X and Y directions.","PeriodicalId":123514,"journal":{"name":"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Surface-tension driven self-assembly for VCSEL chip bonding to achieve 3D and hetero integration\",\"authors\":\"Y. Ito, T. Fukushima, K. Lee, K. Choki, T. Tanaka, M. Koyanagi\",\"doi\":\"10.1109/LTB-3D.2014.6886154\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Self-assembly with liquid surface tension was applied to tiny chips that were difficult to manipulate. Dummy chips that mimics VCSEL were aligned toward hydrophilic sites surrounding a hydrophobic area on an Si interposer. The alignment accuracies were 0 and -2.0 μm in X and Y directions.\",\"PeriodicalId\":123514,\"journal\":{\"name\":\"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LTB-3D.2014.6886154\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LTB-3D.2014.6886154","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Surface-tension driven self-assembly for VCSEL chip bonding to achieve 3D and hetero integration
Self-assembly with liquid surface tension was applied to tiny chips that were difficult to manipulate. Dummy chips that mimics VCSEL were aligned toward hydrophilic sites surrounding a hydrophobic area on an Si interposer. The alignment accuracies were 0 and -2.0 μm in X and Y directions.