可迁移性增强功率CMOS

Jaejune Jang, Jaehyeon Jung, Hoon Chang, Yongdon Kim, Seoin Park, Hyun-Ju Kim, Jaehwan Kim, Sangbae Yi
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引用次数: 1

摘要

本文介绍了通过在130纳米技术上的几何优化来增强移动性的5V CMOS,以实现最先进的RSP性能。通过在(100)晶圆上实现栅格式布局的通道方向,NMOS和PMOS的迁移率都得到了提高,有效宽度也得到了提高。此外,通过引入来自STI附近岛屿的双轴压应力,可以实现更高的迁移率。因此,与标准条形布局相比,NMOS的IDSAT和IDLIN分别提高了24%/29%和29%/37%。所有这些都是在没有任何工艺改变的情况下获得的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Mobility enhanced power CMOS
This paper introduces mobility enhanced 5V CMOS through geometry optimization in 130nm technology for state-of-the-art RSP performance. By realizing <;100> channel direction on (100) wafer with grid-type layout, mobility of both NMOS and PMOS is enhanced in addition to increased effective width. Furthermore even higher mobility is achieved through introduction of biaxial compressive stress from nearby STI islands. As a result, IDSAT and IDLIN increase by 24%/29% for NMOS and 29%/37% for PMOS respectively compared to standard bar-type layout. All of this is obtained without any process change.
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