在测试CMOS打开的一个意想不到的因素:模具表面

Proceedings of 14th VLSI Test Symposium Pub Date : 1900-01-01 DOI:10.1109/VTEST.1996.510888

H. Konuk, F. Ferguson

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引用次数: 32

摘要

我们首次提出了实验证据，表明芯片表面可以作为RC互连，成为决定CMOS开路产生的浮线电压的重要因素。我们提出了一个电路模型，并通过HSPICE仿真验证了这一效果。对这一现象背后的潜在机制进行了详细分析。我们还介绍了在制造过程中沉积在浮栅上的捕获电荷的测量结果。

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An unexpected factor in testing for CMOS opens: the die surface

We present the experimental evidence, for the first time, that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a floating wire created by a CMOS open. We present a circuit model for this effect verified with HSPICE simulations. A detailed analysis of potential mechanisms behind this phenomenon is provided. We also present our measurement results for the trapped charge deposited on floating gates during fabrication.

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Proceedings of 14th VLSI Test Symposium

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