{"title":"低压CMOS工艺中耐高压电源轨ESD箝位电路的设计","authors":"M. Ker, Chang-Tzu Wang, Tien-Hao Tang, K. Su","doi":"10.1109/RELPHY.2007.369967","DOIUrl":null,"url":null,"abstract":"A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.","PeriodicalId":433104,"journal":{"name":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","volume":"94 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes\",\"authors\":\"M. Ker, Chang-Tzu Wang, Tien-Hao Tang, K. Su\",\"doi\":\"10.1109/RELPHY.2007.369967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.\",\"PeriodicalId\":433104,\"journal\":{\"name\":\"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual\",\"volume\":\"94 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2007.369967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2007.369967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
提出了一种新型的容高压电源轨静电放电(ESD)箝位电路，该电路采用1倍vdd器件实现的专用ESD检测电路，用于容三倍vdd混合电压I/O接口。所提出的电源导轨ESD钳位电路具有优异的ESD保护效果，已在仅1.2 v器件的0.13 μ m CMOS工艺中得到验证。
Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes
A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.
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