Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, O. Callen, S. Fabre, R. Ross, P. Simon, Robin Wilson
{"title":"CMOS标准电池产率提高方法","authors":"Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, O. Callen, S. Fabre, R. Ross, P. Simon, Robin Wilson","doi":"10.1109/ISQED.2006.147","DOIUrl":null,"url":null,"abstract":"In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Yield enhancement methodology for CMOS standard cells\",\"authors\":\"Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, O. Callen, S. Fabre, R. Ross, P. Simon, Robin Wilson\",\"doi\":\"10.1109/ISQED.2006.147\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples\",\"PeriodicalId\":138839,\"journal\":{\"name\":\"7th International Symposium on Quality Electronic Design (ISQED'06)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th International Symposium on Quality Electronic Design (ISQED'06)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2006.147\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th International Symposium on Quality Electronic Design (ISQED'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2006.147","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Yield enhancement methodology for CMOS standard cells
In order to maximize the yield of random logic in today's advanced deep sub-micron CMOS technologies we have developed a complete yield enhancement methodology for CMOS standard cells. This methodology based on a test vehicle approach covers design, industrial test, data collection and volume analysis, design debug, failure location and analysis. It has proven to be successful on three consecutive technology nodes down to 65nm. This paper explains the methodology and demonstrate the results and benefits of this work through illustrated examples
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
