{"title":"一种考虑界面态产生的MOSFET栅极电流退化的数值模型","authors":"C. Yih, S.S. Chung, C. Hsu","doi":"10.1109/SISPAD.1996.865301","DOIUrl":null,"url":null,"abstract":"In this paper, a new gate current degradation model for n-MOSFET's by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A numerical model for simulating MOSFET gate current degradation by considering the interface state generation\",\"authors\":\"C. Yih, S.S. Chung, C. Hsu\",\"doi\":\"10.1109/SISPAD.1996.865301\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new gate current degradation model for n-MOSFET's by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.\",\"PeriodicalId\":341161,\"journal\":{\"name\":\"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)\",\"volume\":\"137 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.1996.865301\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.1996.865301","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
In this paper, a new gate current degradation model for n-MOSFET's by considering the interface state generation is proposed. This interface state has been characterized using a new approach and incorporated into a 2D device simulation for predicting the device gate current characteristics due to a hot carrier stress induced effect. Good agreement of the gate current has been achieved as compared with the measurement data for both fresh and stressed devices. This model is not only useful for predicting the gate current degradation, but also as a superior monitor to substrate current for submicron device reliability issues, in particular EPROM or flash EPROM devices.