{"title":"用冲击电离晶体管实现陡峭亚阈值摆幅","authors":"Y. Yeo","doi":"10.1109/VTSA.2009.5159284","DOIUrl":null,"url":null,"abstract":"Recent developments in Impact Ionization Transistors (I-MOS) will be discussed here, including strained impact ionization transistors realized on the nanowire or multiple-gate device architecture. I-MOS devices achieve excellent subthreshold swings well below 5 mV/decade at room temperature. Techniques for enhancing impact ionization rate and reducing the breakdown voltage VBD for device performance improvement will be discussed. Challenges faced by I-MOS will be highlighted. Some challenges may be addressed through the strain and materials engineering. Limitations of the I-MOS will also be discussed.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Realizing steep subthreshold swing with Impact Ionization Transistors\",\"authors\":\"Y. Yeo\",\"doi\":\"10.1109/VTSA.2009.5159284\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent developments in Impact Ionization Transistors (I-MOS) will be discussed here, including strained impact ionization transistors realized on the nanowire or multiple-gate device architecture. I-MOS devices achieve excellent subthreshold swings well below 5 mV/decade at room temperature. Techniques for enhancing impact ionization rate and reducing the breakdown voltage VBD for device performance improvement will be discussed. Challenges faced by I-MOS will be highlighted. Some challenges may be addressed through the strain and materials engineering. Limitations of the I-MOS will also be discussed.\",\"PeriodicalId\":309622,\"journal\":{\"name\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Technology, Systems, and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTSA.2009.5159284\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Technology, Systems, and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2009.5159284","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realizing steep subthreshold swing with Impact Ionization Transistors
Recent developments in Impact Ionization Transistors (I-MOS) will be discussed here, including strained impact ionization transistors realized on the nanowire or multiple-gate device architecture. I-MOS devices achieve excellent subthreshold swings well below 5 mV/decade at room temperature. Techniques for enhancing impact ionization rate and reducing the breakdown voltage VBD for device performance improvement will be discussed. Challenges faced by I-MOS will be highlighted. Some challenges may be addressed through the strain and materials engineering. Limitations of the I-MOS will also be discussed.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
