Dual-K versus dual-T technique for gate leakage reduction: a comparative perspective

As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (dual-K) or use of silicon dioxide of higher thicknesses (dual-T) is being considered as methods for its reduction. This paper presents a comparative view of dual dielectric and dual thickness low leakage design techniques from a behavioral synthesis perspective. An algorithm is presented for the gate leakage current reduction that does simultaneous scheduling, allocation and binding during behavioral synthesis while accounting for process variations. The algorithm minimizes the gate leakage for given time constraints. We performed experiments for a number of benchmark circuits using a 45nm CMOS technology datapath library. We obtained gate leakage reduction as high as 95% for the dual-K (SiO2 and Si3 N4) and 91% for the dual-T (1.4 nm and 1.7 nm) approaches. It is observed that the dual-K approach outperformed the dual-T approach for all benchmark circuits