{"title":"表面态对GaAs功率mesfet影响的数值模拟","authors":"P. Francis, Y. Ohno, M. Nogome, Y. Takahashi","doi":"10.1109/SISPAD.1996.865302","DOIUrl":null,"url":null,"abstract":"Summary form only given. The effects of surface states on the gate offset regions of GaAs power MESFETs are analyzed using a two-dimensional device simulator with a Shockley-Read-Hall statistics model for the surface states. Assuming electron trap type surface states and hole trap type surface states, it is found that the trap properties cause a large difference in DC performance and pulse operation of the FETs.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Numerical simulations of surface states effects on GaAs power MESFETs\",\"authors\":\"P. Francis, Y. Ohno, M. Nogome, Y. Takahashi\",\"doi\":\"10.1109/SISPAD.1996.865302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. The effects of surface states on the gate offset regions of GaAs power MESFETs are analyzed using a two-dimensional device simulator with a Shockley-Read-Hall statistics model for the surface states. Assuming electron trap type surface states and hole trap type surface states, it is found that the trap properties cause a large difference in DC performance and pulse operation of the FETs.\",\"PeriodicalId\":341161,\"journal\":{\"name\":\"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.1996.865302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.1996.865302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Numerical simulations of surface states effects on GaAs power MESFETs
Summary form only given. The effects of surface states on the gate offset regions of GaAs power MESFETs are analyzed using a two-dimensional device simulator with a Shockley-Read-Hall statistics model for the surface states. Assuming electron trap type surface states and hole trap type surface states, it is found that the trap properties cause a large difference in DC performance and pulse operation of the FETs.