J.P. Liu, P. R. Verma, S. Chu, S.Q. Zhang, W. Loh, K. Leong, H.L. Siew, D. Sohn, L. Hsia, S. Decoutere, M. Xu, K. van Wichelen, R. Loo
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引用次数: 2
摘要
我们发现,在0.18 μ m SiGe BiCMOS工艺中加入间隙C会影响SiGe:C HBTs的基极电流理想性。调整生长条件得到的结构和工艺参数相同但间隙C较小的SiGe:C外延层具有较好的基极电流理想性。我们观察到,基极损耗区的间隙C,而不是中性基极区的间隙C,导致基极电流的非理想性。通过优化C取代和构型,可以减少复合,控制B扩散,从而提高器件性能
Impact of Interstitial Carbon on Base Current Ideality in SiGe:C Heterojunction Bipolar Transistors
We show that the incorporation of interstitial C impacts the base current ideality in SiGe:C HBTs fabricated in 0.18mum SiGe BiCMOS process. SiGe:C epi layers with the same structural and processing parameters but with less interstitial C obtained by adjusting growth conditions have better base current ideality. It is observed that the interstitial C in the emitter/base depletion region, rather than that in the neutral base region, leads to the base current non-ideality. Optimization of C substitution and profile leads to less recombination as well as good B diffusion control thus good device performance