M. Yanagisawa, Masataka Watanabe, T. Kawasaki, Hirohiko Kobayashi, K. Kotani, R. Yamabi, Y. Tosaka, D. Fukushi
{"title":"采用全湿蚀刻工艺形成三台面的高可靠性和可重复性InGaAs/InP双异质结双极晶体管","authors":"M. Yanagisawa, Masataka Watanabe, T. Kawasaki, Hirohiko Kobayashi, K. Kotani, R. Yamabi, Y. Tosaka, D. Fukushi","doi":"10.1109/BCTM.2013.6798153","DOIUrl":null,"url":null,"abstract":"The authors have succeeded in making a robust fabrication process applied to InP-based double heterojunction bipolar transistors. The process, featuring all-wet etching method for formation of triple-mesa structure, has shown markedly high reproducibility and reliability. The variation of the current gain has been 4.6% through 130 wafers, and the mean time to failure at the junction temperature of 100°C has been longer than 4 × 106 hours, whose criterion is a 5% change in current gain. These excellent results show that our structure of DHBT, which has an InP passivation layer on the surface of the base layer, and our all-wet mesa formation process, are sufficient to be applied to the manufacturing of integrated circuits.","PeriodicalId":272941,"journal":{"name":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation\",\"authors\":\"M. Yanagisawa, Masataka Watanabe, T. Kawasaki, Hirohiko Kobayashi, K. Kotani, R. Yamabi, Y. Tosaka, D. Fukushi\",\"doi\":\"10.1109/BCTM.2013.6798153\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors have succeeded in making a robust fabrication process applied to InP-based double heterojunction bipolar transistors. The process, featuring all-wet etching method for formation of triple-mesa structure, has shown markedly high reproducibility and reliability. The variation of the current gain has been 4.6% through 130 wafers, and the mean time to failure at the junction temperature of 100°C has been longer than 4 × 106 hours, whose criterion is a 5% change in current gain. These excellent results show that our structure of DHBT, which has an InP passivation layer on the surface of the base layer, and our all-wet mesa formation process, are sufficient to be applied to the manufacturing of integrated circuits.\",\"PeriodicalId\":272941,\"journal\":{\"name\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCTM.2013.6798153\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2013.6798153","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation
The authors have succeeded in making a robust fabrication process applied to InP-based double heterojunction bipolar transistors. The process, featuring all-wet etching method for formation of triple-mesa structure, has shown markedly high reproducibility and reliability. The variation of the current gain has been 4.6% through 130 wafers, and the mean time to failure at the junction temperature of 100°C has been longer than 4 × 106 hours, whose criterion is a 5% change in current gain. These excellent results show that our structure of DHBT, which has an InP passivation layer on the surface of the base layer, and our all-wet mesa formation process, are sufficient to be applied to the manufacturing of integrated circuits.