{"title":"ANSI/ESD S20.20 -下一代标准","authors":"S. Duncan, J. Gibson, T. J. Kinnear","doi":"10.23919/EOS/ESD.2018.8509743","DOIUrl":null,"url":null,"abstract":"As IC technologies evolve in favor of faster IO speeds and increased package sizes, challenging constraints will be placed on future development of on chip ESD protection. Using ANSI/ESD S20.20 as a baseline, this paper will outline critical elements that factories of the future must consider to be successful.","PeriodicalId":328499,"journal":{"name":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"ANSI/ESD S20.20 – The Next Generation\",\"authors\":\"S. Duncan, J. Gibson, T. J. Kinnear\",\"doi\":\"10.23919/EOS/ESD.2018.8509743\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As IC technologies evolve in favor of faster IO speeds and increased package sizes, challenging constraints will be placed on future development of on chip ESD protection. Using ANSI/ESD S20.20 as a baseline, this paper will outline critical elements that factories of the future must consider to be successful.\",\"PeriodicalId\":328499,\"journal\":{\"name\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/EOS/ESD.2018.8509743\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EOS/ESD.2018.8509743","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
As IC technologies evolve in favor of faster IO speeds and increased package sizes, challenging constraints will be placed on future development of on chip ESD protection. Using ANSI/ESD S20.20 as a baseline, this paper will outline critical elements that factories of the future must consider to be successful.
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