小间距晶圆级封装器件的试验台建模和表征

J. Jayabalan, R.D. Mihai, J. Tan, M. Iyer, O. B. Leong, L. M. Seng
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引用次数: 2

摘要

本文描述了一种用于测试小间距晶圆级封装器件的中间体硬件。它是用来处理多千兆赫的信号传播使用100微米间距的GSG探针。对测试硬件插座的所有组件,如SMA连接器、PCB上的共面传输线和蹦床网进行了建模。此外,还测量了一个衬垫上没有凸起的芯片样本。测量和模型表明,测试插座工作在5ghz,插入损耗约为3dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Test bench modeling and characterization for fine pitch wafer level packaged devices
This work describes an interposer hardware for testing fine pitch wafer level packaged devices. It is built to handle multi-gigahertz signal propagation using 100 micron pitch GSG probes. All the components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB and trampoline mesh have been modeled. A sample chip, without bumps on the pads, has also been measured. The measurement and models demonstrate that the test socket performs at 5 GHz with an insertion loss of about 3dB.
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