一种低输入、低功耗的CMOS ADC

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI:10.1109/ISQED.2006.11

Biye Wang, Lili He, Morris Jones

{"title":"一种低输入、低功耗的CMOS ADC","authors":"Biye Wang, Lili He, Morris Jones","doi":"10.1109/ISQED.2006.11","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low input, low-power dissipation CMOS ADC\",\"authors\":\"Biye Wang, Lili He, Morris Jones\",\"doi\":\"10.1109/ISQED.2006.11\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology\",\"PeriodicalId\":138839,\"journal\":{\"name\":\"7th International Symposium on Quality Electronic Design (ISQED'06)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th International Symposium on Quality Electronic Design (ISQED'06)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2006.11\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th International Symposium on Quality Electronic Design (ISQED'06)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2006.11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文设计了一种低输入(0.75 ~ 1.75V)、低功耗的流水线CMOS ADC。8位ADC在2.5V电源电压下消耗78.3mW功率。在195kHz输入频率下，DNL和INL分别为0.6LSB和0.7LSB, SFDR为51.259dB。采用TSMC0.25mum CMOS技术，芯片面积为1.023 mm × 0.795 mm

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A low input, low-power dissipation CMOS ADC

This paper presents the design of a low input (0.75 to 1.75V) and low power dissipation pipelined CMOS ADC. The 8 bits ADC consumes 78.3mW power at 2.5V supply voltage. The DNL and INL are 0.6LSB and 0.7LSB respectively, and SFDR is 51.259dB at 195kHz input frequency. The chip area is 1.023 mm times 0.795 mm with TSMC0.25mum CMOS technology

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7th International Symposium on Quality Electronic Design (ISQED'06)

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