Y. Civale, A. Redolfi, P. Jaenen, M. Kostermans, E. Van Besien, S. Mertens, T. Witters, N. Jourdan, S. Armini, Z. El-Mekki, K. Vandersmissen, H. Philipsen, P. Verdonck, N. Heylen, P. Nolmans, Yunlong Li, K. Croes, G. Beyer, B. Swinnen, E. Beyne
{"title":"三维集成电路制造的硅通孔技术","authors":"Y. Civale, A. Redolfi, P. Jaenen, M. Kostermans, E. Van Besien, S. Mertens, T. Witters, N. Jourdan, S. Armini, Z. El-Mekki, K. Vandersmissen, H. Philipsen, P. Verdonck, N. Heylen, P. Nolmans, Yunlong Li, K. Croes, G. Beyer, B. Swinnen, E. Beyne","doi":"10.1109/IEMT.2012.6521827","DOIUrl":null,"url":null,"abstract":"Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Through-silicon via technology for three-dimensional integrated circuit manufacturing\",\"authors\":\"Y. Civale, A. Redolfi, P. Jaenen, M. Kostermans, E. Van Besien, S. Mertens, T. Witters, N. Jourdan, S. Armini, Z. El-Mekki, K. Vandersmissen, H. Philipsen, P. Verdonck, N. Heylen, P. Nolmans, Yunlong Li, K. Croes, G. Beyer, B. Swinnen, E. Beyne\",\"doi\":\"10.1109/IEMT.2012.6521827\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.\",\"PeriodicalId\":315408,\"journal\":{\"name\":\"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.2012.6521827\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.2012.6521827","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Through-silicon via technology for three-dimensional integrated circuit manufacturing
Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.