{"title":"太级计算——互连在卷计算平台中的作用","authors":"J. Bautista","doi":"10.1109/IITC.2007.382385","DOIUrl":null,"url":null,"abstract":"Future CPU directions are increasingly emphasizing parallel compute platforms which consequently, depend upon greater core to core communication and generally stress the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon bandwidth/latency but must be moderated with power and cost considerations. Motivation, requirements, and potential solutions are summarized briefly in this paper.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Tera-scale Computing - the Role of interconnects in Volume Compute platforms\",\"authors\":\"J. Bautista\",\"doi\":\"10.1109/IITC.2007.382385\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Future CPU directions are increasingly emphasizing parallel compute platforms which consequently, depend upon greater core to core communication and generally stress the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon bandwidth/latency but must be moderated with power and cost considerations. Motivation, requirements, and potential solutions are summarized briefly in this paper.\",\"PeriodicalId\":403602,\"journal\":{\"name\":\"2007 IEEE International Interconnect Technology Conferencee\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Interconnect Technology Conferencee\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2007.382385\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Interconnect Technology Conferencee","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2007.382385","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Tera-scale Computing - the Role of interconnects in Volume Compute platforms
Future CPU directions are increasingly emphasizing parallel compute platforms which consequently, depend upon greater core to core communication and generally stress the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon bandwidth/latency but must be moderated with power and cost considerations. Motivation, requirements, and potential solutions are summarized briefly in this paper.
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