存储器阵列片上互连的性能建模与优化

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2015-12-07 DOI:10.1109/EPEPS.2015.7347150

J. Mohseni, C. Pan, A. Naeemi

{"title":"存储器阵列片上互连的性能建模与优化","authors":"J. Mohseni, C. Pan, A. Naeemi","doi":"10.1109/EPEPS.2015.7347150","DOIUrl":null,"url":null,"abstract":"Performance modeling and optimization for on-chip interconnects in DRAM arrays are presented at various technology generations. Multiple interconnect design schemes and novel interconnect technology options are investigated to minimize the overall delay and energy-delay product.","PeriodicalId":130864,"journal":{"name":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Performace modeling and optimization for on-chip interconnects in memory arrays\",\"authors\":\"J. Mohseni, C. Pan, A. Naeemi\",\"doi\":\"10.1109/EPEPS.2015.7347150\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Performance modeling and optimization for on-chip interconnects in DRAM arrays are presented at various technology generations. Multiple interconnect design schemes and novel interconnect technology options are investigated to minimize the overall delay and energy-delay product.\",\"PeriodicalId\":130864,\"journal\":{\"name\":\"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPS.2015.7347150\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2015.7347150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

在不同的技术世代中，提出了DRAM阵列片上互连的性能建模和优化。研究了多种互连设计方案和新颖的互连技术选择，以最小化总体延迟和能量延迟产品。

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Performace modeling and optimization for on-chip interconnects in memory arrays

Performance modeling and optimization for on-chip interconnects in DRAM arrays are presented at various technology generations. Multiple interconnect design schemes and novel interconnect technology options are investigated to minimize the overall delay and energy-delay product.

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来源期刊

2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS)

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