An analytical model for thermal failure analysis of 3D IC packaging

The analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed for calculating mean die temperature of a 3D IC package. The thermal resistance network model is set up based on heat dissipation paths from multi-die to ambient and is a composite of thermal spreading resistance and one-dimensional (1D) thermal resistance. Thermal spreading resistance comprises the majority of the thermal resistance when heat flows in the horizontal direction of the large plate. The present study investigates the role of determining temperature rise compared to thermal resistances intrinsic to the 3D technology, including thermal resistance of bonding layers and through-silicon-vias (TSVs). As the four thinner stacking chips in the 3D package are connected by TSVs and bumps, the Finite Element method (FEM) analysis is used to analyze the thermal management of the 3D Stacked IC package. The simulation model to obtain the multi-die temperature of 3D IC package was built up by ANSYS® APDL. The data comparison between the simulation and the analytical model showed that the analytical model is matched with the simulation model, demonstrating that the analytical model can be used to predict the thermal failure in 3D IC packages accurately. The main point in this paper is to use a simple concept and theoretical resistance network model to improve the thermal failure by redesigning the parameters or materials of the Printed Circuit Board (PCB).