{"title":"连续时间δ - σ调制器中的时钟抖动抑制技术","authors":"H. Zare-Hoseini, I. Kale","doi":"10.1109/VDAT.2006.258138","DOIUrl":null,"url":null,"abstract":"This paper presents a brief overview and comparison of the most popular techniques used for suppressing the effect of clock-jitter in continuous-time delta-sigma modulators, including multi-bit, FIR, switched-capacitor, sine, and switched-shaped-current digital to analogue converters. Their principles and design issues are presented followed by a performance comparison which provides inform views on the power consumption issues, speed, ease of realization and effectiveness in jitter suppression of the various techniques","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"145 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Clock-Jitter Reduction Techniques in Continuous Time Delta-Sigma Modulators\",\"authors\":\"H. Zare-Hoseini, I. Kale\",\"doi\":\"10.1109/VDAT.2006.258138\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a brief overview and comparison of the most popular techniques used for suppressing the effect of clock-jitter in continuous-time delta-sigma modulators, including multi-bit, FIR, switched-capacitor, sine, and switched-shaped-current digital to analogue converters. Their principles and design issues are presented followed by a performance comparison which provides inform views on the power consumption issues, speed, ease of realization and effectiveness in jitter suppression of the various techniques\",\"PeriodicalId\":356198,\"journal\":{\"name\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"145 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2006.258138\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2006.258138","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Clock-Jitter Reduction Techniques in Continuous Time Delta-Sigma Modulators
This paper presents a brief overview and comparison of the most popular techniques used for suppressing the effect of clock-jitter in continuous-time delta-sigma modulators, including multi-bit, FIR, switched-capacitor, sine, and switched-shaped-current digital to analogue converters. Their principles and design issues are presented followed by a performance comparison which provides inform views on the power consumption issues, speed, ease of realization and effectiveness in jitter suppression of the various techniques
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