分析了fpga面向应用测试的测试生成问题

M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian
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引用次数: 22

摘要

本文的目标是生成一个面向应用的测试程序,供FPGA用户在给定的应用中使用。首先给出了测试基于ram的fpga的具体问题的一般定义,例如“交流非冗余故障”的重要概念。通过在XILINX 4000E上实现的一组电路,表明在电路网络表上执行的经典测试模式生成具有较低的交流非冗余故障覆盖率,并指出需要在FPGA表示上执行测试模式生成。然后证明,通过消除大多数交流冗余故障,在FPGA表示上执行的测试模式生成可以显着加速。最后,提出了一种通过简化FPGA描述来加速测试模式生成过程的技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Analyzing the test generation problem for an application-oriented test of FPGAs
The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault'. Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.
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