Wan Qinfang, Mai Zhihong, Tan Pik Kee, J. Lam, G. Woods, Breeanna Cain, D. Brown, L. Ross
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Backside Fault Isolation Technique in 0.13μm and 90nm Product Prototyping
As IC manufacturing processes move to smaller feature sizes, fault isolation technique and debug become more and more challenging. In this paper, die level backside fault isolation case studies using emission microscope and scanning laser microscope are presented. They efficiently identified the fault sites in 0.13mum and 90nm products