Junki Jang, Kyoung-Woo Park, Chi-Seon Park, S. Yoo, S. Cha, K. Nam, Kihyun Kim, J. Son, Eunyoung Park, Jaeho Lee, Joosung Kim, Miji Lee, M. Yeo, EunJi Jung, R. Kim, Doohwan Park, Chin Kim, Yunki Choi, Taehong Ha, Jeonghoon Ahn, J. Ku
{"title":"用于高性能逻辑器件的具有选择性ALD屏障的极其先进的Cu互连","authors":"Junki Jang, Kyoung-Woo Park, Chi-Seon Park, S. Yoo, S. Cha, K. Nam, Kihyun Kim, J. Son, Eunyoung Park, Jaeho Lee, Joosung Kim, Miji Lee, M. Yeo, EunJi Jung, R. Kim, Doohwan Park, Chin Kim, Yunki Choi, Taehong Ha, Jeonghoon Ahn, J. Ku","doi":"10.1109/IITC/MAM57687.2023.10154689","DOIUrl":null,"url":null,"abstract":"In this paper, selective atomic layer deposition (ALD) TaN barrier process was described for advanced high performance logic device. Compared to conventional ALD deposited barrier, selective barrier adopted process showed 40% lower via resistance and comparable electrical healthiness at various via test structures. By applying this process, we achieved better chip performance and comparable chip yield using internal foundry product. This result demonstrates manufacturability of a selective barrier for advanced high performance logic device. Keywords—Cu; Barrierless, ALD TaN;","PeriodicalId":241835,"journal":{"name":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Extreamly Advanced Cu Interconnect with Selective ALD Barrier for High Performance Logic Device\",\"authors\":\"Junki Jang, Kyoung-Woo Park, Chi-Seon Park, S. Yoo, S. Cha, K. Nam, Kihyun Kim, J. Son, Eunyoung Park, Jaeho Lee, Joosung Kim, Miji Lee, M. Yeo, EunJi Jung, R. Kim, Doohwan Park, Chin Kim, Yunki Choi, Taehong Ha, Jeonghoon Ahn, J. Ku\",\"doi\":\"10.1109/IITC/MAM57687.2023.10154689\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, selective atomic layer deposition (ALD) TaN barrier process was described for advanced high performance logic device. Compared to conventional ALD deposited barrier, selective barrier adopted process showed 40% lower via resistance and comparable electrical healthiness at various via test structures. By applying this process, we achieved better chip performance and comparable chip yield using internal foundry product. This result demonstrates manufacturability of a selective barrier for advanced high performance logic device. Keywords—Cu; Barrierless, ALD TaN;\",\"PeriodicalId\":241835,\"journal\":{\"name\":\"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC/MAM57687.2023.10154689\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC/MAM57687.2023.10154689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Extreamly Advanced Cu Interconnect with Selective ALD Barrier for High Performance Logic Device
In this paper, selective atomic layer deposition (ALD) TaN barrier process was described for advanced high performance logic device. Compared to conventional ALD deposited barrier, selective barrier adopted process showed 40% lower via resistance and comparable electrical healthiness at various via test structures. By applying this process, we achieved better chip performance and comparable chip yield using internal foundry product. This result demonstrates manufacturability of a selective barrier for advanced high performance logic device. Keywords—Cu; Barrierless, ALD TaN;
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