{"title":"使用nmos为中心布局的多单元打乱硬化6T SRAM","authors":"S. Yoshimoto, K. Nii, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/IMFEDK.2013.6602257","DOIUrl":null,"url":null,"abstract":"This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.","PeriodicalId":434595,"journal":{"name":"2013 IEEE International Meeting for Future of Electron Devices, Kansai","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Multiple-cell-upset hardened 6T SRAM using NMOS-centered layout\",\"authors\":\"S. Yoshimoto, K. Nii, H. Kawaguchi, M. Yoshimoto\",\"doi\":\"10.1109/IMFEDK.2013.6602257\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.\",\"PeriodicalId\":434595,\"journal\":{\"name\":\"2013 IEEE International Meeting for Future of Electron Devices, Kansai\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Meeting for Future of Electron Devices, Kansai\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMFEDK.2013.6602257\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Meeting for Future of Electron Devices, Kansai","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMFEDK.2013.6602257","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiple-cell-upset hardened 6T SRAM using NMOS-centered layout
This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67-98% compared with a general macro that has PMOS-centered 6T SRAM cells.
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