Advanced doping and millisecond annealing for ultra-shallow junctions for 65 nm and beyond

To meet the requirements of smaller devices while still maintaining high performance, it is necessary to form very shallow source/drain extensions with very high activation. Although significant progress has been made in meeting these requirements as outlined in the 2003 ITRS, continued progress in meeting the needs for the 65 nm technology generation and beyond remain a challenge. It will no longer be sufficient to consider the doping (ion implantation) and activation (annealing) steps independently. Both must be optimized together as a process sequence or module. This paper will survey the requirements for USJ doping and activation for the 65 nm node and beyond. Some recent results of the annealing of shallow P2LAD-doped silicon wafers using Vortek's fRTP millisecond flash lamp annealing will be presented and some discussion of the extendibility and applicability of these techniques will be presented