A High-pass Filter with On-chip Body Bias Technique for Neural Signals Processing

This manuscript presents a high-pass filter for neural signals processing. An operational transconductance amplifier-capacitor (OTA-C) filter architecture is chosen to decrease the power consumption and the active area. The on-chip body bias technique is adopted to reduce the offset of the bandwidth due to the process, voltage and temperature (PVT) variation. The proposed filter is designed in 40 nm CMOS technology. Simulation results indicate that it has a signal bandwidth located above 300 Hz, dynamic range of 68 dB, and a power consumption of 14 nW at 1.1 V supply.