{"title":"在贴片过程中预测C4非湿性的方法","authors":"V. D. Khanna, S. M. Sri-Jayantha","doi":"10.1109/ECTC.2010.5490842","DOIUrl":null,"url":null,"abstract":"Balancing the level of substrate warp at reflow with other sources contributing to C4 non-wets is an important problem. To address this, a methodology to predict the probability of non-wets during the chip attach process of an organic package has been developed. A technique for quantifying the convex or concave warp of a substrate in the form of a Shape Inversion (SI) plot is introduced. Geometrical factors that influence non-wets such as C4 height, the pad's relative location, collapsed solder height etc. are described and their individual contributions to the non-wet conditions are computed. Combining these contributions onto the SI plot allows for a graphical representation of the non-wet probability. The technique is applied to a product substrate and the results compared with the actual yield observed during chip assembly.","PeriodicalId":429629,"journal":{"name":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Methodology for predicting C4 non-wets during the chip attach process\",\"authors\":\"V. D. Khanna, S. M. Sri-Jayantha\",\"doi\":\"10.1109/ECTC.2010.5490842\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Balancing the level of substrate warp at reflow with other sources contributing to C4 non-wets is an important problem. To address this, a methodology to predict the probability of non-wets during the chip attach process of an organic package has been developed. A technique for quantifying the convex or concave warp of a substrate in the form of a Shape Inversion (SI) plot is introduced. Geometrical factors that influence non-wets such as C4 height, the pad's relative location, collapsed solder height etc. are described and their individual contributions to the non-wet conditions are computed. Combining these contributions onto the SI plot allows for a graphical representation of the non-wet probability. The technique is applied to a product substrate and the results compared with the actual yield observed during chip assembly.\",\"PeriodicalId\":429629,\"journal\":{\"name\":\"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2010.5490842\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2010.5490842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Methodology for predicting C4 non-wets during the chip attach process
Balancing the level of substrate warp at reflow with other sources contributing to C4 non-wets is an important problem. To address this, a methodology to predict the probability of non-wets during the chip attach process of an organic package has been developed. A technique for quantifying the convex or concave warp of a substrate in the form of a Shape Inversion (SI) plot is introduced. Geometrical factors that influence non-wets such as C4 height, the pad's relative location, collapsed solder height etc. are described and their individual contributions to the non-wet conditions are computed. Combining these contributions onto the SI plot allows for a graphical representation of the non-wet probability. The technique is applied to a product substrate and the results compared with the actual yield observed during chip assembly.