{"title":"基于时序仿真的数字CMOS VLSI热载流子退化预测","authors":"E. Minami, K. Quader, P. Ko, C. Hu","doi":"10.1109/IEDM.1992.307419","DOIUrl":null,"url":null,"abstract":"We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation\",\"authors\":\"E. Minami, K. Quader, P. Ko, C. Hu\",\"doi\":\"10.1109/IEDM.1992.307419\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.<<ETX>>\",\"PeriodicalId\":287098,\"journal\":{\"name\":\"1992 International Technical Digest on Electron Devices Meeting\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 International Technical Digest on Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1992.307419\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307419","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation
We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits. The use of a timing simulator enables a quick characterization of degradation in large circuits. The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude.<>
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