高电压InGaN/GaN/AlGaN RTD适用于GaN/InGaN器件和集成电路的ESD保护应用,仿真结果验证

Zhang Haipeng, Geng Lu, Lin Mi, Zhan Zhonghai, Lu Weifeng, Wang Xiaoyuan, Wang Ying, Zhang Qiang, B. Jianling, Wang Dejun
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引用次数: 0

摘要

提出了一种用于GaN/InGaN器件和集成电路ESD保护的新型高压InGaN/GaN/AlGaN RTD。所提出的RTD由一个夹在GaN/InGaN衬底上的$\text{In}_{0.21}\text{Ga}_{0.79}\mathrm{N}/\text{GaN}/\text{In}_{0.14}\text{Ga}_{0.86}\mathrm{N}/\mathrm{a} 1_{0.1}\text{Ga}} {0.9}\mathrm{N}$ DBS结构组成。仿真实验表明,所提出的RTD样品具有7.38 V左右的高正向阻挡电压、小于10^{-38}\ mathm {A}/\mu \ mathm {m}^{2}$和小于10^{-39}\ mathm {A}/\mu \ mathm {m}^{2}$的低漏正向电流和大于10^{-4}\ mathm {A}/\mu \ mathm {m}^ 2}$的高反向电流密度。对HBM型ESD电路的分析表明,HBM型ESD电路可以简化为理想的一阶RC回路。这是因为无论是否考虑其寄生电容,所提出的高压(HV) RTD对在导通状态时的电阻相对于放电电阻R1是可以忽略的。因此,结面积为$120 × 120\mu \ mathm {m}^{2}$的样品1足够大,可以在理想的840 ns内保护芯片免受高达$ $ pm 2000$ V ESV的ESD损坏。对于样品2,其结面积$380\乘以$380\ mu \ mathm {m}^{2}$能够提供与样品1相同的ESD保护强度。通过分析样品2的发射极区、量子阱区和集电极区在偏置电压下的电荷变化,考虑了样品2的寄生电容,结果表明,量子区的大信号差分寄生浮动电容约为-0.178/-0.174 pF/cm2,与HBM模式ESD保护应用的标准ESV电容相比可以忽略不计。它的作用是屏蔽外加电压对量子阱电位的影响。其电压衰减系数不大于−23.6 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High Voltage InGaN/GaN/AlGaN RTD Suitable for ESD Protection Applications of GaN/InGaN-based Devices and ICs Validated by Simulation Results
A novel high voltage InGaN/GaN/AlGaN RTD was proposed for ESD protection of GaN/InGaN-based devices and ICs. The proposed RTD consists of a sandwiched $\text{In}_{0.21}\text{Ga}_{0.79}\mathrm{N}/\text{GaN}/\text{In}_{0.14}\text{Ga}_{0.86}\mathrm{N}/\mathrm{A}1_{0.1}\text{Ga}_{0.9}\mathrm{N}$ DBS structure on a GaN/InGaN substrate with N-original surface. Simulation experiments indicated that the proposed RTD samples are characterized of high forward block voltages at about 7.38 V, low leakage forward currents less than $10^{-38}\mathrm{A}/\mu \mathrm{m}^{2}$ and $10^{-39}\mathrm{A}/\mu \mathrm{m}^{2}$ and high reverse current densities up to the order of $10^{-5}\mathrm{A}/\mu \mathrm{m}^{2}$ at about −2.55 V bias voltage and beyond $10^{-4}\mathrm{A}/\mu \mathrm{m}^{2}$ at about −2.8 V bias voltage respectively. Analysis on HBM mode ESD circuits indicated that they can be simplified into ideal one order RC loop. This is because that the resistance of the proposed high voltage (HV) RTD pair at on-state is ignorable relative to discharging resistance R1 whether considering its parasitic capacitance or not. As a result, the sample 1 with junction area of $120\times 120\mu \mathrm{m}^{2}$ is large enough to protect the chip from ESD damaging up to $\pm 2000$ V ESV swash in ideal 840 ns. As for sample 2, its junction area of $380\times 380\mu \mathrm{m}^{2}$ is capable of providing the same strength of ESD protection as that of sample 1. As the parasitic capacitance of sample 2 was considered through analyses of charge variations in emitter region, quantum well region and collector region with bias voltage, the results indicate that the big signal differential parasitic floating capacitance of quantum region is about -0.178/-0.174 pF/cm2, which is negligible comparing with stand ESV capacitance of HBM mode ESD protection applications. Its function is to shielding the influence of applied voltage on the potential of the quantum well. Its attenuation factor of voltage is not more than −23.6 dB.
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