一种高密度圆柱形MIM电容器，集成了先进的28nm逻辑高k /金属门工艺，用于嵌入式DRAM

Proceedings of Technical Program of 2012 VLSI Technology, System and Application Pub Date : 2012-04-23 DOI:10.1109/VLSI-TSA.2012.6210164

K. Tu, C. Wang, Y. Hsieh, Y. Ting, C. Chang, C. Pai, K. Tzeng, H. Chu, H. L. Lin, Y. Chang, C. Pen, K. W. Chen, T. Hsieh, C. Tsai, K. C. Huang, W. Chiang, M. Wang, C. Wang, C. Tsai, S. Wuu, H. Hwang, L. Tran

{"title":"一种高密度圆柱形MIM电容器，集成了先进的28nm逻辑高k /金属门工艺，用于嵌入式DRAM","authors":"K. Tu, C. Wang, Y. Hsieh, Y. Ting, C. Chang, C. Pai, K. Tzeng, H. Chu, H. L. Lin, Y. Chang, C. Pen, K. W. Chen, T. Hsieh, C. Tsai, K. C. Huang, W. Chiang, M. Wang, C. Wang, C. Tsai, S. Wuu, H. Hwang, L. Tran","doi":"10.1109/VLSI-TSA.2012.6210164","DOIUrl":null,"url":null,"abstract":"A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A high density cylinder-type MIM capacitor integrated with advanced 28nm logic High-K/Metal-Gate process for embedded DRAM\",\"authors\":\"K. Tu, C. Wang, Y. Hsieh, Y. Ting, C. Chang, C. Pai, K. Tzeng, H. Chu, H. L. Lin, Y. Chang, C. Pen, K. W. Chen, T. Hsieh, C. Tsai, K. C. Huang, W. Chiang, M. Wang, C. Wang, C. Tsai, S. Wuu, H. Hwang, L. Tran\",\"doi\":\"10.1109/VLSI-TSA.2012.6210164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.\",\"PeriodicalId\":388574,\"journal\":{\"name\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2012.6210164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

采用先进的28nm逻辑高k /金属栅极(HKMG)工艺，研制了一种用于嵌入式DRAM的圆柱形金属-绝缘体-金属(MIM)电容器。堆叠电池电容器采用低温高k介电体形成，在不显著影响逻辑晶体管的情况下实现足够的存储电容。本文介绍了实现圆柱形MIM电容器电容> 10fF/cell并保持低漏损(10年)的技术。测试飞行器由72个宏组成，每个宏大小为4.5Mb。我们成功地展示了全功能良好的28nm eDRAM 324Mb测试车，访问速度>;330MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A high density cylinder-type MIM capacitor integrated with advanced 28nm logic High-K/Metal-Gate process for embedded DRAM

A cylinder-type Metal-Insulator-Metal (MIM) capacitor integrated with advanced 28nm logic High-K/Metal-Gate (HKMG) process for embedded DRAM has been developed. The stacked cell capacitor is formed using low temperature high-K dielectrics to achieve sufficient storage capacitance without significantly impacting logic transistors. This paper describes techniques to achieve cylinder-type MIM capacitor's capacitance >;10fF/cell and keep the low leakage (<;0.1fA/cell) requirements. The MIM dielectric reliability test passes Time Dependent Dielectric Breakdown (TDDB) lifetime (>;10 years). The test vehicle is composed of 72 macros of 4.5Mb each. We successfully demonstrate fully functional good yield of 28nm eDRAM 324Mb test vehicle with access speed >;330MHz.

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Proceedings of Technical Program of 2012 VLSI Technology, System and Application

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