{"title":"纳米技术时代电路设计的内置可靠性分析","authors":"Zhihong Liu, Weiquan Zhang, Fuchen Mu","doi":"10.1109/ICICDT.2004.1309946","DOIUrl":null,"url":null,"abstract":"In this paper, the methodology of the reliability modeling and simulation for the state-of-the-art technology is presented. The extraction for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method is discussed. The integration of these models into the transistor level and gate level simulation flow can be used by the designers to satisfy the reliability requirements.","PeriodicalId":158994,"journal":{"name":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Build-in reliability analysis for circuit design in the nanometer technology era\",\"authors\":\"Zhihong Liu, Weiquan Zhang, Fuchen Mu\",\"doi\":\"10.1109/ICICDT.2004.1309946\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the methodology of the reliability modeling and simulation for the state-of-the-art technology is presented. The extraction for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method is discussed. The integration of these models into the transistor level and gate level simulation flow can be used by the designers to satisfy the reliability requirements.\",\"PeriodicalId\":158994,\"journal\":{\"name\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT.2004.1309946\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2004.1309946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Build-in reliability analysis for circuit design in the nanometer technology era
In this paper, the methodology of the reliability modeling and simulation for the state-of-the-art technology is presented. The extraction for HCI (Hot Carrier Injection) and NBTI (Negative Bias Temperature Instability) for both lifetime and aged model parameter method is discussed. The integration of these models into the transistor level and gate level simulation flow can be used by the designers to satisfy the reliability requirements.