A New Dielectric Breakdown Mechanism In Silicon Dioxides

A new dielectric breakdown mechanism is proposed on the basis of the profile of stress-induced defect sites in the oxide. This model well explains the oxide thickness dependence of “B mode” stress-induced leakage current(B-SILC) and is valid for thicker oxides where the B-SILC is not observed. The model indicates that the stress relaxation of oxide and the smoothening of the SiO,/Si interface roughness are key issues to realize future ultrathin gate oxidcs ( d n m ) with high reliability. Introduction Highly reliable ultrathin gate oxide plays an important rolein achieving advanced MOS LSIs. It is strongly required to reveal the oxide breakdown mechanism, in particular, in the ultrathin oxides. Recently, Degraeve et al. proposed a model to link two generally-accepted models[l][2] in the ultrathin oxides[3][4]. In their model, breakdown is defined as the conduction via electron traps from one interface to the other. However the conduction mechanism has not been clarified. In the ultrathin oxides, we have reported the “B mode” stressinduced leakage current (B-SILC)[S] and clarified to be the variable range hopping (VRH) conduction[6][7], which is mediated by the defect sites, including various trap sites and interface states. The breakdown process is divided into the “partial breakdown” which induces the B-SILC, and the “complete breakdown”[8][9]. These are invaluable information to clarify the oxide breakdown mechanism. In this paper, we propose a new dielectric breakdown mechanism which is valid for the whole oxide thickness range. Experimental 4nm and 6.5nmthick oxides were grown in 0, atmosphere at 800°C on CZ-p type Si (100) substrates The electrical characteristics were measured using conventional MOS capacitors or mercury probing method. Electrons were injected from the gate electrode to the oxide. Results and Discussions A . In Figs. 1 and 2, curves from a to e show typical degradation behavior of 4nm-thick oxides by electrical stress plotted in semi-log and linear scale, respectively. After the “A mode” SILC[10] (curve b), the B-SILC appears at a local spot (curve c). By calculating d 3 x c, we can find in Fig.2 thc linear relationship between gate current and voltage as shown in line d’ which indicates the ohmic conduction. Since the plural B-SILC appears at different local spots@], curve d is found to be just a sum of three B-SILCs and ohmic conduction at different local spots as shown in the inset of Fig. 2. By further stress, the ohmic current increases since the resistance decreases (curve e). The B-SILC implies the intermediate state in the oxide breakdown sequence. B. Clarification of Defect Site Profile expressed as a function of temperature T[6] ; Denradation Behavior of Ultrathin Oxides In the VRH conduction of the B-SILC, the current I is I ( r ) = A exp(-B T (1) B = 2.06 (a’ N ) (2) where k, is the Boltzmann’s constant a and N is the decay length and density of the defect sites available for carrier conduction, respectively. According to (1) and (2), the BSILC does not depend on the oxide thickness, Tox, but depends only on a3N in (2). The B-SILC is plotted in Fig.3 as a function of Tox. Although the B-SILC does not depend on Tox, it slightly decreases as Tox becomes thicker than -4.8nm. ‘I’he B-SILC is not observed when Tox>-5.5 nm. Thus, the profile d defect sites in the oxide should be considered as a function of the distance from the SiO,/Si interface. 6.Snm-thick oxides were etched to various thickness by diluted HF solution after various electrical stress. Fig.4 shows a typical current-voltage characteristics before (curve A) and after (curves B, C) etched to 4.4nm. Although the B-SILC was not observed before the etching (curve A), the B-SILC clearly appears after the etching (curve C). Even after etched to 3.1 nm, the B-SILC is still observed. This indicates: (i) the originof B-SILC is the same as that of oxide breakdown, and (ii) BSILC is not observed in thicker oxides because of difficulty in generating defect sites in oxide far from the SiO,/Si interface. C. According to ( 1 ) and ( 2 ) , the B-SILC is limited by the minimum a3N through the conduction path and larger a3N corresponds to the larger B-SILC. A model of a3N as a function of the distance from the SiOJSi interface is shown in Fig. S, where L, is the minimum threshold for the B-S IT ,C to he observed. Key points are: (i) a3N gradually decreases as the distance becomes larger, and (ii) d N becomes smaller in the vicinity of the SiO,/Si interface (ToxD,). In the case shown in Fig.3, Do < 2.5 nm, D, = 4.8 nm and D? = 5.5 nm. Fig.6 shows the model for the four step oxide breakdown sequence, that is; (i) defect sites having the profile shown in Fig.5 are generated, (ii) VRH conduction appears when a3N reaches a critical value, ( i i i ) defect sites are further generated, and (iv) ohmicconduction path is formedfollowed by further resistance lowering. Stages (ii) and (iv) are “partial breakdown” and “complete breakdown”, respectively, in ultrathin oxides. Although stage (ii) does not appear in thicker oxides because of the defect site profile as shown in big.5, the breakdown mechanism is the same. The complete breakdown occurs when a3N in the vicinity of the interface reaches a critical value, since the time to complete breakdown after partial breakdown strongly depends on the interface roughness[S][S]. Although stage (ii) is defined as the breakdown in Degraeve’s model, stage (iv) should be defined as the breakdown, because the BSILC is not observed in thicker oxides. This allows an unique definition of breakdown in the whole oxide thickness range. From the above consideration, the stress relaxation of oxide and the smoothening of the SiO,/Si interface roughness are considered to be key issues to realize future ultrathin oxides. Model for Dielectric Breakdown Mechanism 143 4-93081 3-75-1 197 1997 Symposium on VLSl Technology Digest of Technical Papers Conclusion A new dielectric breakdown mechanism is proposed, which well explains the typical characteristics of B-SILC in ultrathin oxides and its oxide thickness dependence. This rnodel is also valid for the whole oxide thickness range (>-,2.5nm). Based on this model, the stress relaxation of oxide and the smoothening of the Si02/Si interface roughness are pointed out to tie key issues to realize future ultrathin gate oxides (<5nm) with high reliability. Acknowledgment The author thanks Dr. T. Takemoto, Dr. M. Oguraarid Dr. S. MKyumi for their encouragement and K. Eriguchi for his invaluable discussions. He also thanks S. Kawasaki and G. Sugahara for their help. 0 1 2 3 4 Gate Voltage [-VI Fig.1 Typical degradation behavior of 4nm-thick oxides by Fowler Nordheim (F-N) stress plotted in semi-log scale. 0 1 2 3 4 Gate Voltage [-VI Fig.2 by F-N stress plotted in linear scale. Typical degradation behavior of 4nm-thick oxides 3 4 5 Oxide Thickness [nm] Fig..? Oxide thickness dependence of the B-SILC (4V) and the F-N tunneling current (-6V). I n the thickness range thicker than about 5.51" the B-SILC is not observed. Refmnces [I]J.C.Lee, I.C. ChenandC. Hu,IEEEElec.Dev.35 (1988)2268. [ 2 ] E Avni and J. Shappir, J. Appl. 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