Design aspects for CPI robust BEOL

In this paper we present our methodology to establish a quantitative comparison of the induced stresses at different locations of the package and their effect on the strength of the back-end-of-line (BEOL). A Chip Stack Package (CSP) with tight pitch and lead free solder joints is used as test vehicle. Different configurations of the interconnection between the solder balls and the BEOL, including a stiff passivation layer combined with a polyimide stress buffer layer with different thickness and openings are analyzed. It was found that the bending moment of the outermost solder joint induces high tensile stresses in the BEOL layer and this stress is reduced by increasing the thickness of the passivation layer. For this particular case, an optimal geometry of the stress buffer, in terms of thickness and open diameter is proposed. The stresses and energy release rate (ERR) induced on the BEOL is analyzed in a 2 metal layer configuration with different densities of via interconnections. The strength of the BEOL is improved when increasing both, the stiffness of the low-k material and the density of vias.